1. Field of the Invention
The invention relates to clock data recovery and, in particular, to clock data recovery circuits with phase decision circuits.
2. Description of the Related Art
Some data streams, especially high-speed serial data streams, (such as the raw stream of data from the magnetic head of a disk drive) are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and phase-aligns to the transitions in the data stream with a phase locked loop (PLL). In order for this scheme to work, the data stream must have frequent enough transition to correct any drift in the PLL's oscillator. Thus, clock data recovery circuits can be a key circuit block in a receiver.
FIG. 1 shows a conventional clock data recovery circuit as disclosed in “A 0.5 um CMOS 4 Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling”, IEEE J. Solid-State Circuits, vol. 33, pp 713-722, May. 1998, by C. K. Yang and M. Horowitz. The clock data recovery circuit comprises a sampler 110, an XOR circuit block 120, a shift register 130, a voter 140, a multiplexer 150 and a post process logic circuit 160. The sampler 110 receives an input data stream IN and a sampling clock signal CLK. The XOR circuit 120 is coupled to the sampler 110 and receives the oversampled input data stream IN′. The shift register 130 is coupled to the XOR circuit block 120. The voter 140 is coupled to the shift register 130 and generates a voting result according to the oversampled input data stream IN′. The multiplexer 150 is coupled to the voter 140 and selects data from the oversampled input data stream IN′ according to the voting result. Data processing of the selected data is performed by the post process logic circuit 160 and thus an output signal is provided. In this conventional clock data recovery circuit, number of voting needs to be large enough such that voting error rate is reduced. Hardware cost is also an issue.
FIG. 2 shows another conventional clock data recovery circuit as disclosed in “Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling”, IEEE Communication Magazine, pp. 68-74, December 2003, by J. Kim and D. K. Jeong. The clock data recovery circuit comprises a sampler 210, an XOR circuit block 220, a first voter 230, a shift register 240, a second voter 250, a multiplexer 260 and a post process logic circuit 270. The sampler 210 receives an input data stream IN and a sampling clock signal CLK. The XOR circuit 220 is coupled to the sampler 210 and receives the oversampled input data stream IN′. The first voter 230 is coupled to the XOR circuit block 220 and performs a first voting. The shift register 240 is coupled to the first voter 230 and receives the first voting result. The second voter 250 is coupled to the shift register 240 and generates a second voting result according to an output signal of the shift register 240. The multiplexer 260 is coupled to the second voter 250 and selects data from the oversampled input data stream IN′ according to the second voting result. Data processing of the selected data is performed by the post process logic circuit 270 and thus an output signal is provided. In this conventional clock data recovery circuit, number of voting still needs to be large enough such that voting error rate is reduced. Hardware cost, while lower than in the previous conventional clock data recovery circuit, remains an issue.